Parasitic capacitance, resistance and inductance effects are becoming more pronounced with the advent of deep submicron process technologies. Even though the processing technology advancements in copper interconnect and low-k dielectric materials reduce parasitic resistance and capacitance, the need to accurately account for parasitic effects is growing as circuit speeds and density continue to increase. Parasitic extraction generates circuit models and plays an important role in various aspects of physical verification such as timing, signal noise, substrate noise, and power grid analysis.
Parasitic extraction requires solving some form of Maxwell's equations with layout design and process profile data. Semiconductor manufacturers, however, usually do not want to supply original layout design and process profile data for devices such as transistors due to the risk of disclosing their proprietary technologies. To facilitate parasitic extraction, electrically equivalent models for devices are usually provided instead. FIG. 1a illustrates an example of cross section of a transistor design. The process for fabricating the gate 110 of the transistor 100 may be inferred from the corresponding layout design and process profile data. FIG. 1b illustrates an example of cross section of an electrically equivalent model 120 for the gate 110 shown in FIG. 1a. Even though the model 120 has a different structure compared to the gate 110, the transistor 130 approximates the electrical characteristics of the transistor 100 and thus can be used to replace the transistor 100 in circuits for extracting parasitic circuit models.
The electrically equivalent model illustrated in FIG. 1b is a simplified electrically equivalent model obtained in part by changing the dielectric constant values. While particularly useful in some situations, a simplified electrically equivalent model may not meet the requirement of high-accuracy parasitic extraction. This is especially true in the advanced technology modes. It is thus desirable to search for techniques that can generate more accurate electrically equivalent models for devices or layout features.